The present disclosure relates to a semiconductor device and a flash-memory control method. For example, the present disclosure relates to a control technique that is used when a plurality of masters perform writing/erasing processes for a flash memory.
A type of a semiconductor device including a plurality of masters (e.g., a plurality of master processing units) may be configured so that the plurality of masters use one common flash memory. In a semiconductor device having such a configuration, for example, a memory controller controls access to the flash memory from each of the masters.
Japanese Unexamined Patent Application Publication No. 2008-34045 discloses a technique for interrupting/resuming a writing/erasing process for a flash memory.
In general, when a certain master is performing a writing/erasing process for a flash memory, other masters cannot perform any of reading, writing, and erasing processes for that flash memory. It should be noted that it takes time to write/erase data to/from a flash memory. Therefore, in some cases, when a certain master is performing a writing/erasing process for a flash memory as described above, other masters cannot access the flash memory for a long time and need to wait a long time.
To solve the above-described problem, Japanese Unexamined Patent Application Publication No. 2008-34045 discloses a semiconductor device in which even when a writing/erasing process is being performed for a flash memory, this writing/erasing process can be interrupted so that other processes (e.g., a reading, writing, or erasing process) can be performed for the flash memory.